IRIS Trademark

Trademark Overview

On Monday, January 10, 2005, a trademark application was filed for IRIS with the United States Patent and Trademark Office. The USPTO has given the IRIS trademark a serial number of 78545120. The federal status of this trademark filing is ABANDONED - AFTER INTER-PARTES DECISION as of Saturday, September 29, 2007. This trademark is owned by VESTA Technology, Inc.. The IRIS trademark is filed in the Computer & Software Products & Electrical & Scientific Products category with the following description:

Semiconductor Manufacturing Process Modules for use in Atomic Layer Deposition
iris

General Information

Serial Number78545120
Word MarkIRIS
Filing DateMonday, January 10, 2005
Status604 - ABANDONED - AFTER INTER-PARTES DECISION
Status DateSaturday, September 29, 2007
Registration Number0000000
Registration DateNOT AVAILABLE
Mark Drawing4000 - Illustration: Drawing with word(s) / letter(s) / number(s) in Block form
Published for Opposition DateTuesday, December 12, 2006

Trademark Statements

Goods and ServicesSemiconductor Manufacturing Process Modules for use in Atomic Layer Deposition

Classification Information

International Class009 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments; apparatus and instruments for conducting, switching, transforming, accumulating, regulating or controlling electricity; apparatus for recording, transmission or reproduction of sound or images; magnetic data carriers, recording discs; automatic vending machines and mechanisms for coin operated apparatus; cash registers, calculating machines, data processing equipment and computers; fire extinguishing apparatus.
US Class Codes021, 023, 026, 036, 038
Class Status Code8 - Abandoned
Class Status DateSaturday, September 29, 2007
Primary Code009
First Use Anywhere DateFriday, December 17, 2004
First Use In Commerce DateTuesday, December 28, 2004

Trademark Owner History

Party NameVESTA Technology, Inc.
Party Type20 - Owner at Publication
Legal Entity Type03 - Corporation
AddressSan Jose, CA 95135
Party NameVESTA Technology, Inc.
Party Type10 - Original Applicant
Legal Entity Type03 - Corporation
AddressSan Jose, CA 95135

Trademark Events

Event DateEvent Description
Friday, October 19, 2007UNDELIVERABLE MAIL - NO ACTION TAKEN
Monday, October 1, 2007ABANDONMENT NOTICE MAILED - INTER PARTES DECISION
Saturday, September 29, 2007ABANDONMENT - AFTER INTER PARTES DECISION
Saturday, September 29, 2007OPPOSITION SUSTAINED NO. 999999
Tuesday, June 19, 2007OPPOSITION INSTITUTED NO. 999999
Tuesday, January 9, 2007EXTENSION OF TIME TO OPPOSE RECEIVED
Tuesday, December 12, 2006PUBLISHED FOR OPPOSITION
Wednesday, November 22, 2006NOTICE OF PUBLICATION
Friday, October 20, 2006LAW OFFICE PUBLICATION REVIEW COMPLETED
Friday, October 13, 2006ASSIGNED TO LIE
Monday, October 9, 2006APPROVED FOR PUB - PRINCIPAL REGISTER
Thursday, October 5, 2006TEAS/EMAIL CORRESPONDENCE ENTERED
Monday, September 25, 2006CORRESPONDENCE RECEIVED IN LAW OFFICE
Monday, September 25, 2006TEAS RESPONSE TO OFFICE ACTION RECEIVED
Wednesday, July 12, 2006CONTINUATION OF FINAL REFUSAL MAILED
Wednesday, July 12, 2006ACTION CONTINUING A FINAL - COMPLETED
Tuesday, July 11, 2006TEAS/EMAIL CORRESPONDENCE ENTERED
Thursday, June 22, 2006CORRESPONDENCE RECEIVED IN LAW OFFICE
Thursday, June 22, 2006TEAS RESPONSE TO OFFICE ACTION RECEIVED
Tuesday, April 18, 2006FINAL REFUSAL MAILED
Tuesday, April 18, 2006FINAL REFUSAL WRITTEN
Wednesday, April 12, 2006PETITION TO REVIVE-GRANTED
Monday, March 27, 2006PETITION TO REVIVE-RECEIVED
Monday, March 27, 2006PAPER RECEIVED
Wednesday, March 8, 2006ABANDONMENT NOTICE MAILED - FAILURE TO RESPOND
Wednesday, March 8, 2006ABANDONMENT - FAILURE TO RESPOND OR LATE RESPONSE
Wednesday, February 1, 2006ASSIGNED TO EXAMINER
Wednesday, August 10, 2005NON-FINAL ACTION MAILED
Tuesday, August 9, 2005NON-FINAL ACTION WRITTEN
Tuesday, August 9, 2005ASSIGNED TO EXAMINER
Friday, January 21, 2005NEW APPLICATION ENTERED IN TRAM

Related Keywords

iris layer deposition atomic modules manufacturing process semiconductor